The execution of program instructions typically requires a sequential execution of various operations directly related to the instruction, such as instruction fetch, decode, execute and result read/store. Pipelined processors allocate specific hardware elements to each of these operations, and sequentially process succeeding instructions so that each of the hardware elements associated with the various instruction operations function constantly albeit for two or more separate instructions. For an instruction having four separate operation stages which may be sequentially performed in time, a pipeline processor would incorporate four separate hardware elements, each to specifically provide the operation corresponding to the four operation stages of the instruction. A first instruction would be received by the first element to provide a first operation during the first time cycle. A second element would perform the second operation of the first instruction while the first element would acquire the next instruction to provide the first operation of the second instruction. Two cycles subsequently, a fourth element is processing the fourth operation on the first instruction, the third element is providing the third operation on the second instruction, the second element is providing the second operation on the third instruction and the first element is providing the first operation on the fourth instruction. The pipeline processing continues as long as instructions are sequentially received by the processor pipeline or until an exception is generated by one of the four elements of the pipeline processor. The exceptions relate to an unacceptable condition resulting from the processing of a particular instruction, such as page fault, a register overflow, or other condition of invalid data or instructions. While exceptions may occur at any point in the execution of an instruction, the most severe exception recovery requirement occurs when the exception is indicated in the later cycles of the instruction execution.
The number of cycles necessary to execute an instruction is dependent on the particular instruction. The instruction set may comprise instructions which require the same number of execution cycles, or may include instructions requiring varying numbers of execution cycles resulting in a corresponding variability in the number of processor execution elements. When an exception occurs, the processor inhibits the subsequent execution of the instruction which provoked the exception, services the exception and restarts that instruction and any subsequent instructions. However, processors having variable length instruction execution times face a condition where an exception may be generated by a long execution cycle instruction (long instruction) which began before a subsequent, shorter execution cycle instruction (shorter instruction). When the exception occurs, the subsequent, shorter instruction may have completed its execution and modified the corresponding registers with the proper information. However, in the condition that the exception occurs after the completed execution of the shorter instruction, the known exception handling techniques would require that the instruction that provokes the exception, as well as the completed shorter instruction and any subsequent instruction be re-executed. The result would be multiple execution shorter instructions producing erroneous computation. Consequently, the implementation of pipeline processors to service variable execution length instructions has been held in disfavor, or the variability of the instruction execution cycles is strictly controlled to avoid the above-mentioned condition of completed execution of a subsequently begun, shorter instruction. Such design considerations impose unnecessary limitations in computer architecture, function and efficiency.